Voltage regulator that operates in either PWM or PFM mode

ABSTRACT

A switching voltage regulator achieves high efficiency by automatically switching between a pulse frequency modulation (PFM) mode and a pulse-width modulation (PWM) mode. Switching between the modes of voltage regulation is accomplished by monitoring the output voltage and the output current, wherein the regulator operates in PFM mode at small output currents and in PWM mode at moderate to large output currents. PFM mode maintains a constant output voltage by forcing the switching device to skip cycles when the output voltage exceeds its nominal value. In PWM mode, a PWM signal having a variable duty cycle controls the switching device. A constant output voltage is maintained by feedback circuitry which alters the duty cycle of the PWM signal according to fluctuations in the output voltage.

FIELD OF THE INVENTION

The present invention relates to a voltage regulator. More specifically,the present invention relates to a high efficiency switching voltageregulator capable of operating in either one of two modes.

BACKGROUND OF THE INVENTION

Typically, voltage regulator circuits provide a constant output voltageof a predetermined value by monitoring the output and using feedback tokeep the output constant. In a typical pulse width modulation (PWM)regulator circuit, a square wave is provided to the control terminal ofthe switching device to control its on and off states. Since increasingthe on time of the switching device increases the output voltage, andvice versa, the output voltage may be controlled by manipulating theduty cycle of the square wave. This manipulation is accomplished by acontrol circuit which continually compares the output voltage to areference voltage and adjusts the duty cycle of the square wave tomaintain a constant output voltage.

When the switching device is an MOS transistor, a significant amount ofpower is used to periodically charge the gates of the switchingtransistors. As the switching frequency increases, more power is lost.If the switching frequency is too low and the output current of theregulator is high, the output voltage of the regulator will be difficultto filter and convert to a DC voltage. Hence, the switching frequencymust be kept relatively high. When the output current is low, therelatively high power loss due to controlling the switching transistorsresults in a low efficiency (output power/total power consumed)regulator.

A continuing challenge in the design of voltage regulators is to reducethe power loss in the regulator circuit and thereby increase itsefficiency. As such, the power dissipate dissipated in the controlcircuitry and switching circuitry of the PWM regulator is of greatconcern.

SUMMARY OF THE INVENTION

A switching voltage regulator is disclosed which is capable of operatingin either a pulse frequency modulation (PFM) or pulse-width modulation(PWM) mode. The voltage regulator achieves high efficiency byautomatically choosing the more efficient mode of regulation based on acontinuous monitoring of the output current and the output voltage. Theregulator operates in PFM mode when the regulator generates a smalloutput current and switches to PWM operation when the regulatorgenerates a moderate to large output current.

A PFM mode of voltage regulation provides better efficiency at smalloutput current levels than does a PWM mode. First, a PFM mode requires afewer turn-on transitions to maintain a constant output voltage thandoes a PWM mode of voltage regulation, thus resulting in a lowergate-drive power dissipation for PFM mode. Second, since a PFM mode canbe achieved with a much simpler control circuit having fewer components,the power dissipation in the control loop of a PFM mode is less thanthat of the control loop of a PWM mode.

However, when the output current reaches a moderate level, a PFM mode ofvoltage regulation becomes impractical, since the maximum output currentavailable from a PFM mode is generally much less than that availablefrom a PWM mode. Thus, the present invention switches from a PFM mode ofoperation to a PWM mode of operation when the output current exceeds apredetermined level.

A novel technique to determine when to operate in PWM or PFM mode isalso described along with a novel PFM type voltage regulator.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of one embodiment of the presentinvention;

FIG. 2A is a pictorial representation of the PWM control signal;

FIG. 2B is a pictorial representation of the inductor current during PWMmode of voltage regulation;

FIGS. 3A and 3B are pictorial representations of the output switchvoltage and the inductor current during PFM mode of voltage regulation,respectively;

FIGS. 4A-4C are pictorial representations of the inductor current,switching node voltage, and feedback voltage during PFM mode of voltageregulation;

FIG. 5 is FIGS. 5A-5D illustrate a gate level schematic of oneembodiment of the present invention;

FIG. 6A shows the inductor current during both PFM mode and PWM mode;and

FIGS. 6B-6E are timing diagrams showing the logic states of variouscomponents in the preferred embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIG. 1 is a simplified block diagram of an embodiment of the presentinvention. The voltage regulator of FIG. 1 includes a feedback circuit2, output voltage sensing circuit 3, inductor current sensing circuit 4,control logic circuit 5, PWM control circuit 6, PFM control circuit 7,high-side switch driver 8, low-side switch driver 9, input terminal 10,high-side switch 11, switching node 12, low-side switch 13, schottkydiode 14, inductor 15, capacitor 16, and output terminal 17.

High-side switch 11 is preferably a P-channel MOSFET that has a firstterminal connected to input terminal 10 and a second terminal connectedto a terminal (switching node 12) of inductor 15. The other terminal ofinductor 15 is connected to output terminal 17.

PWM control circuit 6, which includes a PWM signal generator, has anoutput terminal connected to a first input terminal of the high-sideswitch driver 8. The output terminal of PWM control circuit 6 is alsoconnected to the low-side switch driver 9. The output terminal ofhigh-side switch driver 8 is connected to the control terminal ofhigh-side switch 11 for supplying a voltage to turn switch 11 on andoff. Similarly, the output terminal of low-side switch driver 9 isconnected to the control terminal of low-side switch 13, which ispreferably an N-channel MOSFET, for supplying a voltage to turn switch13 on and off. A schottky diode 14 is placed in parallel with low sideswitch 13 for shunting current to ground when current discharging frominductor 15 forces switching node 12 below approximately −0.4 volts.

Feedback circuit 2 is coupled between output terminal 17 and a firstinput terminal of PWM control circuit 6 for providing a feedback signalto PWM control circuit 6. This feedback signal is also provided to afirst input terminal of PFM control circuit 7. PFM control circuit 7 hasa second input terminal connected to switching node 12 for sensing thevoltage V_(sw) at switching node 12 and has an output terminal connectedto a second input terminal of high-side switch driver 8 for controllingthe on and off states of switch 11.

Output voltage sensing circuit 3 has an input terminal connected tooutput terminal 17 and an output terminal connected to a first inputterminal of control logic circuit 5.

Inductor current sensing circuit 4 has an input terminal connected toswitching node 12 and an output terminal connected to a second inputterminal of control logic circuit 5 and to a third input terminal of PFMcontrol circuit 7. An output terminal of control logic circuit 5 isconnected to a second input terminal of PWM control circuit 6 and to afourth input terminal of PFM control circuit 7. Control logic circuit 5enables/disables PWM control circuit 6 and PFM control circuit 7, thusdetermining in which mode the regulator will operate.

Capacitor 16 is coupled between output terminal 17 and ground and actsto smooth the voltage at output terminal 17.

The operation of the regulator is as follows. When an input voltageV_(in) to be regulated is supplied to the regulator circuit via inputterminal 10, the voltage at output terminal 17, V_(out), is initiallybelow its nominal value, V_(out,nom). Output voltage sensing circuit 3detects the low value of V_(out) and sends a logic low signal to controllogic circuit 5, which in turn enables PWM control circuit 6 anddisables PFM control circuit 7. This state is denoted as PWM mode.

Once in PWM mode, PWM control circuit 6 generates and transmits a fixedfrequency square wave to the first inputs of high-side switch driver 8and low-side switch driver 9 which, as mentioned previously, control theon and off states of switches 11 and 13. A high PWM signal turnshigh-side switch 11 on and turns low-side switch 13 off. Conversely, alow PWM signal turns high-side switch 11 off and turns low-side switchon. Operating switches 11 and 13 in a push-pull fashion allows inductor15 to store current from input terminal 10 when switch 11 is on anddischarge current to output terminal 17 when switch 11 turns off.

FIG. 2A illustrates a PWM square wave signal having a period of T. ThisPWM signal has an on-time (representing a logic high) from t=0 to t=DTand an off-time (representing a logic low) from t=DT to t=T, where theduty cycle of the signal is defined as the ratio of on-time to period T.

A feedback voltage V_(fb) corresponding to V_(out) is coupled to PWMcontrol circuit 6 via feedback circuit 2. PWM control circuit 6 comparesV_(fb) to a reference voltage V_(ref) and adjusts the duty cycle of thePWM square wave signal such that V_(fb) is equal to V_(ref).

PWM control circuit 6 continues to control switches 11 and 13 until thepeak current flowing through inductor 15, denoted as I_(ind,pk), dropsbelow a predetermined level, I_(pk,min). When I_(ind,pk) drops belowI_(pk,min), inductor sensing circuit 4 sends a first enabling signal tocontrol logic circuit 5. If output voltage sensing circuit 3 detectsthat V_(out) has not dropped below the regulated output voltage value,output voltage sensing circuit 3 sends a second enabling signal tocontrol circuit 5, which then simultaneously disables PWM controlcircuit 6 and enables PFM control circuit 7. When PWM control circuit 6is disabled, low-side switch 13 is turned off and will remain off untilPWM control circuit 6 is re-enabled. This state is known as PFM mode.

FIG. 2B illustrates the inductor current during PWM mode. Therelationship between I_(pk,min) and I_(out,min) is set by the followingequation:

I_(out,min)=I_(pk,min)−ΔI_(ind)/2   (1)

It can be seen from the above equation that detecting I_(pk,min)accurately corresponds to detecting a constant value of I_(out,min) aslong as the change in ΔI_(ind) remains small relative to I_(pk,min). IfΔI_(ind) changes substantially compared to I_(pk,min), then I_(pk,min)must change in equal proportion to changes in ΔI_(ind) in order forI_(out,min) to remain constant.

Referring back to FIG. 1, when the regulator circuit begins operating inPFM mode, PFM control circuit 7 sends an activation signal to high-sideswitch driver 8, thus turning on switch 11. As mentioned earlier, switch13 remains in an off state during PFM mode. Switch 11 will remain onuntil the inductor current I_(ind) charges to an upper limit,I_(Lim,PFM). When inductor current sensing circuit 4 detects that thislimit has been reached, inductor current sensing circuit 4 sends ade-activation signal to high-side switch driver 8, thereby turningswitch 11 off. The inductor current I_(ind) then discharges throughschottky diode 14, causing the voltage at switching node 12, V_(sw), toswing from approximately V_(in) to −0.4V. When I_(ind) reaches a zerolevel, V_(sw) changes abruptly from −0.4V to V_(out). PFM controlcircuit 7 detects this abrupt increase in V_(sw) and turns on switch 11.Thus, when operating in PFM mode, the regulator circuit monitors theinductor current and the voltage at switching node 12 to determine whento turn on and off high-side switch 11. This PFM mode of voltageregulation is advantageous over others since an internal oscillator isnot required.

PFM control circuit 7 regulates V_(out) by controlling the on and offstates of switch 11 and by preventing switch 11 from turning on whenV_(out) exceeds its predetermined nominal value, V_(out,nom), asfollows. PFM control circuit 7 includes a comparator which comparesfeedback signal V_(fb), which is proportional to V_(out), to referencevoltage V_(ref), V_(ref) has an upper value V_(ref,H) and a lower valueV_(ref,L). If V_(fb) is less than V_(ref,H) PFM control circuit 7 willturn on switch 11 as described in the previous paragraph. If, however,V_(fb) exceeds V_(ref,H) (corresponding to V_(out) exceedingV_(out,nom)), V_(ref) will fall to V_(ref,L), causing PFM controlcircuit 7 to turn switch 11 off. V_(fb) must then fall below V_(ref,L)before PFM control circuit 7 again turns on switch 11. This method ofregulating the V_(out) by preventing switch 11 from turning on whenV_(out), exceeds its nominal value V_(out,nom) is commonly referred toas “skipping cycles”. The PFM characteristic of the reference voltageV_(ref) prevents the regulator from sporadically skipping cycles.

FIGS. 3A and 3B illustrate the waveforms of the voltage at switchingnode 12, V_(sw), and the inductor 15 current, I_(ind), where t_(on) isthe on time of switch 11, t_(off) is the off time of switch 11,I_(ind,avg) is the time average value of I_(ind), and td=the delay timebetween I_(ind) discharging to zero and high-side switch 11 turning on.The above parameters are defined by the following equations:$\begin{matrix}{I_{{ind},{avg}} = {\frac{L_{{Lim},{PFM}}( {t_{OR} + t_{off}} )}{2( {t_{on} + t_{off} + {td}} )} = \frac{I_{{Lim},{PFM}}}{2}}} & {{Eq}.\quad 2} \\{t_{on} = \frac{I_{{Lim},{PFM}} \cdot L}{V_{i} - V_{out}}} & {{Eq}.\quad 3} \\{t_{off} = {\frac{I_{{Lim},{PFM}} \cdot L}{V_{out} + {0.4V}} + {td}}} & {{Eq}.\quad 4}\end{matrix}$

It can be seen from FIG. 3B that the average value of the inductorcurrent waveform I_(ind,avg) is a function of only L_(Lim,PFM), assumingthat td is relatively small compared to the switching period. The valuesof t_(on) and t_(off) will vary as function of V_(in), V_(out), and theinductance L of inductor 15.

When the regulator is supplying maximum current to output terminal 17 inPFM mode, switch 11 turns on at every switching cycle. Therefore, themaximum output current the regulator can supply when operating in PFMmode, I_(ind,avg), will always be equal to I_(Lim,PFM)/2 irrespective ofthe values of V_(in), V_(out), and L. This circuit is thus advantageousover previous methods of PFM mode regulation whose maximum outputcurrents are dependent upon input voltage, output voltage, andinductance values.

The regulator circuit monitors V_(out), to determine when to switch fromPFM mode to PWM mode as follows. When the output current exceeds themaximum current the regulator is able to supply in PFM mode, i.e., whenI_(out) exceeds I_(Lim,PFM)/2, V_(out) falls below V_(out,nom). Outputvoltage sensing circuit 3 detects this change in V_(out), and sends alogic low signal to control logic circuit 5. In response to this lowsignal, control logic circuit 5 sends a disable signal to PFM controlcircuit 7 and an enable signal to PWM control circuit 6, thus switchingthe circuit from PFM mode to PWM mode.

In order to make a clean transition between PFM and PWM modes ofoperation, the following conditions must be met: (1) the output sensingcircuit 3 has a slow enough response time to ensure that brief negativetransients at V_(out) do not trigger an erroneous change from PFM to PWMmode, (2) when the regulator changes from PFM to PWM mode, the controllogic circuit 5 forces the regulator to remain in PWM mode while the PWMcontrol loop settles out (otherwise, during this period control logiccircuit 5 may detect I_(ind,pk) falling below I_(pk,min) for brieftransients, thereby causing the regulator to oscillate between PWM andPFM operation), and (3) the PFM current limit (I_(Lim,PFM)) is greaterthan twice the value of the minimum output current required for PWMoperation (I_(out,min)) (this condition ensures that the maximum outputcurrent for PFM mode (I_(Lim,PR)/2) is greater than I_(out,min). IfI_(Lim,PFM)/2 is less than or equal to I_(out,min), the regulator willoscillate between PFM and PWM modes).

The PFM mode of operation described above varies when the differencebetween V_(in) and V_(out) is approximately 1 volt or less and theoutput current is less than I_(Lim.PFM). FIGS. 4A, 4B, and 4C illustratethe current of inductor 15 (I_(ind)), the voltage at switching node 12(Vsw), and the output of feedback circuit 2, respectively, when theregulator is operating in PFM mode in this particular situation. Sinceunder these conditions I_(ind) never exceeds I_(Lim,PFM), inductorcurrent sense circuit 4 does not cause PFM control circuit 7 to turnswitch 11 off. Thus, as described previously, switch 11 will remain onuntil V_(fb) exceeds V_(ref,H), at which point PFM control circuit 7causes switch 11 to turn off. Inductor 15 then discharges throughschottky diode 14, causing V_(sw) to swing from approximately V_(in) to−0.4V. When I_(ind) reaches a zero level, V_(sw) abruptly changes from−0.4V to V_(out). However, switch 11 remains off until V_(fb) fallsbelow V_(ref,L). PFM control circuit 7 then causes switch 11 to turn on.I_(ind) will then increase, but it will never exceed I_(Lim,PFM).Therefore, switch 11 remains on until V_(fb) rises above V_(ref,H).

Thus, the present invention achieves high efficiency over a wide rangeof output currents by automatically switching between PFM mode operation(when the output current is relatively small) and PWM mode operation(when the output current exceeds a predetermined level).

FIG. 5 is FIGS. 5A-5D illustrate a gate-level schematic of oneembodiment of the present invention. When power is first applied to theregulator circuit at V_(in), V_(out), is below its nominal value,V_(out,nom). This is detected by comparator 174 which sends a logic highsignal to the gate of switch 178, turning on switch 178. The drain ofswitch 178 then swings low, forcing the output of SR latch 138 highwhich, in turn, enables the PWM controller 140. This The high signalfrom latch 138 is received by invertor 164, and invertor 164 thussupplies a low signal to NOR gate 166. The high signal from latch 138 isalso supplied to NAND gate 142. The high signal from latch 138 alsodisables the PFM control circuit by forcing the output of NOR gate 202low. Thus, the circuit initially operates in PWM mode and will remain inPWM mode as long as the peak inductor current I_(ind,pk) is equal to orgreater than the minimum current required for PWM mode, I_(pk,min). WhenI_(ind,pk) drops below I_(pk,min), the regulator switches to PFM mode aspreviously described.

PWM controller 140 generates a fixed frequency square wave PWM signalwith a variable duty cycle. When the PWM signal is high (rising edge), alogic low signal appears at the output of invertor 170, turning offlow-side switch 13. This high PWM signal also puts a logic high at theinput of pulse circuit 151, which turns on switch 150 long enough topull down the input of invertor 156, thus turning on switch 11. Switch150 is used to turn on switch 11 during PWM mode, while switch 152 isused to turn on switch 11 during PFM mode.

Positive feedback is applied to inverters 154 and 156 so that the outputof invertor 156 will remain low after switch 150 (PWM mode) or switch152 (PFM mode) turns off. It is important that switches 150 and 152 turnoff as soon as possible to ensure that switches 146, 148, and 200 canreset the output of invertor 156 to a logic low to turn off switch 11.Hence, switches 150 and 152 must be turned on with a relatively narrowpulse at the beginning of the PWM and PFM switching cycles,respectively.

Pulse circuits 151 (PWM mode) and 153 (PFM mode) detect a leading edgefrom the outputs of invertor 144 and nor gate 160, respectively, andgenerate a positive pulse approximately 200 nanoseconds long at thegates of switches 150 and 152, respectively. This pulse turns onswitches 150 and 152 just long enough to set the output of invertor 156high, thereby turning on high-side switch 11.

When the PWM signal is low (falling edge), switch 146 pulls down theinput of invertor 154, turning off switch 11. This low PWM signal alsoprovides a logic high at the input of NAND gate 168, allowing low-sideswitch 13 to turn on when V_(sw) swings low to −0.4V. Specifically, thelow PWM signal from PWM controller 140 and the high signal from latch138 are supplied to NAND gate 142, NAND gate 142 thus supplies a highsignal to invertor 144, and invertor 144 thus supplies a low signal toNOR gate 166. The high signal from latch 138 is supplied to inventor164, and inventor 164 thus supplies a low signal to NOR gate 166, andNOR gate 16 thus supplies said logic high at the input of NAND gate 168.This method of turning on switch 13 results in break-before-makeswitching of switches 11 and 13. Switch 11 remains off and switch 13remains on until the beginning of the next PWM cycle.

Error amplifier 176 monitors V_(out), during PWM operation by measuringthe difference between the V_(fb) and V_(ref) (V_(out) appears acrossresistors 184, 186 which, acting as a voltage divider, generate V_(fb)at node 185). This voltage difference is amplified and provided as inputto PWM controller 140. PWM controller 140 uses this amplified voltagedifference to adjust the duty cycle of the PWM signal so that V_(fb)equals V_(ref), thereby regulating V_(out). PWM controller 140 can beeither a voltage mode or current mode controller. In order to achievemaximum efficiency when the regulator is operating in PFM mode, PWMcontroller 140 and error amplifier 176 remain off during PFM mode.

The regulator indirectly senses the current of inductor 15 by monitoringthe drain to source voltage V_(ds) of switch 11. When switch 11 is on,switch 102 connects the drain of switch 11 to the inputs of comparators122 and 124. When switch 11 is off, switch 104 shorts the inputs ofcomparators 122 and 124 to the input voltage V_(in). In order toeliminate the noise at the leading edge of the V_(ds) waveform whenswitch 11 is turned on, capacitor 108 and resistor 112 keep switch 102off and switch 104 on until switch 11 has been on approximately 200nanoseconds. When switch 11 turns off, diode 114 allows switch 102 toturn off and switch 104 to turn on immediately.

Comparator 122 causes high-side switch 11 to turn off when the peakinductor current I_(ind,pk) has exceeded the current limit for PWM mode(I_(lim,pwm)) and PFM mode (I_(Lim,PFM)). Comparator 122 monitorsI_(ind,pk) by comparing the V_(ds) of switch 11 to V_(ds) of switch 116.In one embodiment, switch 11 is a power MOSFET constructed of thousandsof small MOSFET cells connected in parallel. Switch 116 is one of thoseMOSFET cells with its drain separated from the drain of switch 11.Switch 116 has an area factor of 1 (1 cell), while switch 11 has an areafactor of K (K cells).

When the regulator operates in PFM mode, switch 126 is off, allowingonly current source 132 to flow through switch 116. Current source 132is set equal to I_(Lim,PFM)/K so that the V_(ds) of switch 116 equalsthe V_(ds) of switch 11 when I_(ind) equals I_(Lim,PFM). In other words,when the regulator is operating in PFM mode, the threshold voltage ofcomparator 122 corresponds to I_(Lim,PFM).

When the regulator is operating in PWM mode, switch 126 turns on toallow both current sources 130 and 132 to flow through switch 116.Current source 130 is set to a value so that the sum of current sources130 and 132 equals I_(Lim,pwm)/K. Thus, the threshold voltage ofcomparator 122 corresponds to I_(Lim,pwm) when the regulator isoperating in PWM mode.

Comparator 124, monitoring the peak inductor current I_(ind,pk) bycomparing the V_(ds) of switch 11 with the V_(ds) of switch 118.Determines when the regulator should switch from PWM mode to PFM mode.Like switch 116, switch 118 is a single MOSFET cell (having an areafactor of 1) with its drain separated from the drain of switch 11.Current source 128 provides a current through switch 118 equal toI_(pk,min)/K, so that the V_(ds) of switch 11 equals the V_(ds) ofswitch 118 when I_(ind) reaches the value I_(pk,min). The value ofI_(pk,min) is adjusted by a multiplier circuit so that it changes inproportion to changes in V_(in)-V_(out). This allows I_(pk,min) tochange in proportion to changes in ΔI_(ind) which, as shown in equation1, results in I_(out,min) remaining constant.

Accordingly, if the peak inductor current I_(ind,pk) is greater thanI_(pk,min), the regulator remains in PWM mode. Referring to FIG. 6A,this event corresponds to time period A. Comparator 124 outputs a logiclow which in turn produces a logic low at the output of SR latch 134.The output of latch 134 remains low until reset to logic high by thefalling edge of the PWM signal (see FIG. 6B). When switch 11 turns off,the rising edge of the inverted PWM signal appears at the clock input ofmaster-slave D flip-flop 136 (see FIG. 6C). The inverted PWM signal isinverted again and used as the reset signal for latch 134. Due to thetime delay of invertor 163 and latch 134, the rising edge of the clockinput of flip-flop 136 occurs before the output of latch 134 is reset toa logic high. Under the conditions of time period A, the output offlip-flop 136 is set to a logic high and remains high so long asI_(ind,pk) exceeds I_(pk,min) (see FIG. 6D). The logic high output fromflip-flop 136 has no effect on the previously set high output of SRlatch 138 (see FIG. 6E).

The logic high signal at the output of latch 138 turns on PWM controller140 and error amplifier 176, as well as allowing the PWM signal topropagate through NAND gate 142, thereby enabling PWM operation. Thehigh signal from the output of latch 138 also turns on switch 126,re-setting the threshold voltage of comparator 122 to a valuecorresponding to I_(lim,pwm). Furthermore, the high signal from theoutput of latch 138 prevents PFM control signals from propagatingthrough NOR gate 202. By setting the threshold of comparator 122 toI_(lim,pwm) and preventing PFM control signals from propagating throughNOR gate 202, PFM mode operation is thereby disabled.

If the inductor current I_(ind) is equal to or exceeds I_(lim,pwm), theoutput of comparator 122 transitions to a logic high, turning on switch148. Switch 148 pulls down the input of invertor 120. Which turns offswitch 11. The positive feedback of weak inverters 154 and 156 keeps theoutput of 156 low after switch 148 turns off so that switch 11 willremain off until the next rising edge of the PWM signal.

When I_(ind,pk) is less than I_(pk,min) (corresponding to time period Bin FIG. 6A), the regulator enters PFM mode. The output of comparator 124and the output of latch 134 remain at logic high when the PWM cycle ends(see FIG. 6B), causing the output of flip-flop 136 to transition tologic low (see FIG. 6D). The logic low signal at the output of flip-flop136 sets the output of latch 138 low (see FIG. 6E), which will remainlow until reset to logic high by switch 178. This low signal from latch138 turns off PWM controller 140 and error amplifier 176, and itprevents the PWM signal from propagating through NAND gate 142, therebydisabling the PWM control circuit. The low signal from latch 138 alsoenables PFM control signals to propagate through NOR gate 202. Inaddition, the low signal from the output of latch 138 turns off switch126, resetting the threshold voltage of comparator 122 to a valuecorresponding to I_(Lim,PFM). In other words, a low signal from theoutput of latch 138 switches the regulator from PWM mode to PFM mode.

Once in PFM mode, the on and off states of high-side switch 11 arecontrolled as described previously. Assuming that switch 11 is initiallyon, current flows through inductor 15 to output terminal 17. When theinductor current I_(ind) exceeds I_(Lim,PFM), comparator 122 turns offswitch 11. I_(ind) then discharges through diode 14, causing V_(sw) todrop to −0.4 volts. When I_(ind) discharges to zero, causing V_(sw) toswing to V_(in), invertor 158 sends a logic low signal to NOR gate 160which, in turn, puts a logic high at the input of pulse circuit 153.Pulse circuit 153, generating a brief turn on pulse at the gate ofswitch 152, causes switch 11 to turn on and thereby starts a newswitching cycle.

The regulator will skip cycles when V_(out) exceeds its nominal valueV_(out,nom). Comparator 172 monitors V_(out) by comparing V_(fb) toV_(ref). When V_(fb) is greater than V_(ref), comparator 172 puts alogic high at an input of NOR gate 160, thereby preventing switch 11from turning on in response to the signal swing of V_(sw) via invertor158. The logic high signal from comparator 172 also propagates throughinvertor 204 and NOR gate 202 so as to turn on switch 200, which causesswitch 11 to turn off. Thus, high-side switch 11, turning off when theoutput voltage has exceeded its nominal value, will turn back on (whenI_(ind) discharges to zero) only if the output voltage has dropped toless than or equal to its nominal value. As explained earlier, V_(fb)exhibits hysteresis to prevent the regulator from sporadically skippingcycles. Preferably, comparator 172 exhibits hysteresis at its inputterminals of approximately 10 mV.

As mentioned previously, a variation of PFM mode operation occurs when(1) the difference between V_(in) and V_(out) is approximately 1 volt orless and (2) the output current is less than I_(Lim,PFM). Since underthese conditions the inductor current never exceeds I_(Lim,PFM), theoutput of comparator 122 will remain at logic low and thus never turnoff switch 11. When V_(out) exceeds V_(out,nom), the logic high outputof comparator 172 turns on switch 200 which, in turn, causes switch 11to turn off. The regulator then stops delivering current to output node17. The output of comparator 172 will remain at logic high until V_(out)falls below V_(out,nom). When the output of comparator 172 hastransitioned to logic low, and I_(ind) has discharged to zero, invertor158 sends a logic low signal to NOR gate 160 which, in turn, causespulse circuit 153 to generate a brief output pulse that turns onhigh-side switch 11. The regulator again supplies current to outputterminal 17. As a result, the regulator maintains a constant outputvoltage by supplying current from V_(in) to output terminal 17 whenV_(out) is less than or equal to V_(out,nom). Accordingly, when V_(out)is exceeds V_(out,nom), the regulator does not supply current fromV_(in) to output terminal 17. Thereby allowing this current to dischargethrough capacitor 16 until V_(out) again falls below V_(out,nom).

The regulator switches from PFM mode back to PWM mode when the outputcurrent exceeds I_(Lim,PFM)/2, which causes V_(out) to fall belowV_(out,nom). This drop in V_(out), is detected by comparator 174, whosethreshold voltage is set to a value about four percent below V_(ref).Thus, when V_(out) falls approximately four percent below V_(out,nom),the output of comparator 174 transitions to a logic high, turning onswitch 182 and thereby resetting latch 138. The logic high at the outputof latch 138 re-enables the PWM control circuit and disables the PFMcontrol circuit, as described earlier.

The PWM signal, when re-enabled, may take one hundred or more cycles tosettle out. During this period, the inductor current will fluctuatecausing I_(ind,pk) to dip below I_(pk,min) for brief transients. Toprevent the regulator from oscillating between PWM and PFM modes duringthese brief transients, the regulator keeps the reset input of latch 138low for a predetermined amount of time after PWM controller 140 has beenre-enabled, as follows. After the regulator re-enters PWM mode, and theoutput of comparator 174 transitions to a logic low, current source 182requires several hundred microseconds to pull-up the reset input oflatch 138 to a logic high. Accordingly, this time delay forces theregulator to remain in PWM mode for several hundred microseconds afterPWM mode is re-enabled.

While particular embodiments of the present invention have been shownand described, it will be obvious to those skilled in the art thatchanges and modifications may be made without departing from thisinvention in its broader aspects and, therefore, the appended claims areto encompass within their scope all such changes and modifications asfall within the true spirit and scope of this invention.

What is claimed is:
 1. A method performed by a switching regulatorcomprising the steps of: generating a regulated output voltage and anoutput current at an output terminal of said regulator using a switchingdevice, said switching device having an on state and an off state, saidswitching device providing said output current; comparing one or moresignals corresponding to said output current to one or more thresholdcurrent levels, said one or more threshold current levels correspondingto predetermined output current levels; generating one or more firstcontrol signals in response to said step of comparing; controlling saidswitching device with a first control circuit in response to said one ormore first control signals indicating said output current is greaterthan a first current level, wherein said first control circuitcomprises: a square wave generator outputting a square wave having afirst frequency and having a duty cycle corresponding to said regulatedoutput voltage at said output terminal, said square wave generatorcontrolling the on and off states of said switching device; and a firstfeedback circuit for generating an error signal based on a differencebetween a voltage corresponding to said output voltage at said outputterminal and a first reference voltage level and varying the duty cycleof said square wave generator in response to said error signal to causesaid output voltage to be of a predetermined voltage level; andcontrolling said switching device with a second control circuit inresponse to said one or more first control signals indicating saidoutput current is less than said first current level by a predeterminedamount, wherein said second control circuit comprises: a signalgenerator outputting a switching signal having afixed a fixed duty cycleand having a second frequency, said signal generator controlling the onand off states of said switching device, wherein said second frequencyis less than said first frequency; and a second feedback circuit forgenerating a disable signal when said output voltage at said outputterminal exceeds a second reference voltage level, said disable signalforcing said signal generator to skip one or more cycles to cause saidoutput voltage to be of said predetermined voltage level.
 2. The methodof claim 1 wherein said predetermined amount is zero.
 3. The method ofclaim 1 wherein said predetermined amount is greater than zero.
 4. Themethod of claim 1 further comprising the steps of: comparing said outputvoltage at said output terminal with a third reference voltage level;generating a second control signal in response to said step of comparingsaid output voltage; and controlling said switching device with saidfirst control circuit in response to said second control signalindicating said output voltage at said output terminal is less than saidthird reference voltage level.
 5. The method of claim 1 wherein saidswitching device comprises a first MOSFET device; said one or moresignals corresponding to said output current in said step of comparingbeing determined by comparing a voltage at a terminal of said firstMOSFET device to one or more threshold voltage levels, said thresholdvoltage levels corresponding to said predetermined output currentlevels.
 6. The method of claim 5 wherein said threshold voltage levelsinclude a voltage at a terminal of a second MOSFET device havingcharacteristics substantially identical to said first MOSFET device,said second MOSFET device conducting a fixed reference current.
 7. Themethod of claim 1, wherein the switching device supplies the outputcurrent via an inductor; and wherein the duty cycle of the switchingsignal is fixed at least in part by an inductance of said inductor. 8.The method of claim 1, wherein the duty cycle of the switching signal isfixed by at least one of an inductance of said inductor through whichthe switching device supplies the output current, an input voltage thatreceives regulation by said method, and the regulated output voltage. 9.The method of claim 1, wherein the signal generator controls duration ofon and off states of the switching signal responsive to at least one ofan inductance of said inductor through which the switching devicesupplies the output current, an input voltage that receives regulationby said method, and the regulated output voltage.